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 SSM2030GM
N- and P-channel Enhancement-mode Power MOSFETs
Simple drive requirement Lower gate charge Fast switching characteristics
Pb-free; RoHS compliant.
D2 D1 D2 D1 D1 D1 G2 G2 S2 G1 S2 S1 G1 S1 D2
N-CH BV DSS R DS(ON) ID P-CH BVDSS RDS(ON) ID
D1
20V 30m 6A -20V 50m -5A
D2
SO-8
DESCRIPTION
Advanced Power MOSFETs from Silicon Standard provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness.
The SSM2030GM is in an SO-8 package, which is widely preferred for commercial and industrial surface mount applications. This device is suitable for low voltage applications requiring complementary N and P MOSFETs.
G1
G2 S1 S2
ABSOLUTE MAXIMUM RATINGS
Symbol VDS VGS I D @ TA=25C ID @ TA=70C IDM PD @ TA=25C TSTG TJ Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Pulsed Drain Current
1,2 3 3
Rating N-channel 20 8 +6 +4.8 +20 2.0 0.016 -55 to 150 -55 to 150 P-channel -20 8 -5 -4 -20
Units V V A A A W W/C C C
Continuous Drain Current Total Power Dissipation Linear Derating Factor
Storage Temperature Range Operating Junction Temperature Range
THERMAL DATA
Symbol Rthj-amb Parameter Thermal Resistance Junction-ambient Max. Value 62.5 Unit C/W
2/10/2005 Rev.2.01
www.SiliconStandard.com
1 of 11
SSM2030GM
N-channel ELECTRICAL CHARACTERISTICS @ Tj = 25o C
Symbol BVDSS Parameter Drain-Source Breakdown Voltage Test Conditions VGS=0V, ID=250uA
(unless otherwise specified)
Min. 20 0.5 -
Typ. 0.037
Max. Units -
V V/C m m V S uA uA nA nC nC nC ns ns ns ns pF pF pF
BV DSS/ Tj
RDS(ON)
Breakdown Voltage Temperature Coefficient Reference to 25C, ID=1mA
Static Drain-Source On-Resistance
VGS=4.5V, ID=6A VGS=2.5V, ID=5.2A
18.5 9 1.8 4.2 300 255 115
30 45 1.2 1 25 100 29 65 60 50 -
VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss
Gate Threshold Voltage Forward Transconductance
Drain-Source Leakage Current (Tj=25 C) Drain-Source Leakage Current (Tj=70 C)
o o
VDS=VGS, ID=250uA VDS=10V, ID=6A VDS=20V, VGS=0V VDS=16V, VGS=0V VGS=8V ID=6A VDS=10V VGS=4.5V VDS=10V ID=1A RG=6, VGS=4.5V RD=10 VGS=0V VDS=8V f=1.0MHz
Gate-Source Leakage Total Gate Charge
2
Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance
2
SOURCE-DRAIN DIODE
Symbol IS ISM VSD Parameter
Continuous Source Current ( Body Diode )
Test Conditions VD=VG=0V , VS=1.2V
1
Min. -
Typ. 0.75
Max. Units 1.7 20 1.2 A A V
Pulsed Source Current ( Body Diode )
Forward On Voltage
2
Tj=25C, IS=1.7A, VGS=0V
Notes:
1.Pulse width limited by max. junction temperature. 2.Pulse width <300us , duty cycle <2%. 3.Surface mounted on FR4 board, t<10sec.
2/10/2005 Rev.2.01
www.SiliconStandard.com
2 of 11
SSM2030GM
P-channel ELECTRICAL CHARACTERISTICS @ Tj = 25 C
Symbol BVDSS
BV DSS/Tj
o
(unless otherwise specified)
Parameter Drain-Source Breakdown Voltage Static Drain-Source On-Resistance Gate Threshold Voltage Forward Transconductance
Drain-Source Leakage Current (T oC) j=25 Drain-Source Leakage Current (T oC) j=70
Test Conditions VGS=0V, ID=250uA VGS=-4.5V, ID=-2.2A VGS=-2.5V, ID=-1.8A VDS=VGS, ID=-250uA VDS=-10V, ID=-2.2A VDS=-20V, VGS=0V VDS=-16V, VGS=0V VGS= 8V ID=-2.2A VDS=-6V VGS=-4.5V VDS=-10V ID=-2.2A RG=6 ,VGS=-4.5V RD=4.5 VGS=0V VDS=-15V f=1.0MHz
Min. -20 -0.5 -
Typ. -0.037
Max. Units 50 80 -1 -1 -25 100 10 25 50 30 V V/C m m V S uA uA nA nC nC nC ns ns ns ns pF pF pF
Breakdown Voltage Temperature Coefficient Reference to 25C, ID=-1mA
RDS(ON) VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss
2.5 11.5 3.2 1.5 940 440 130
Gate-Source Leakage Total Gate Charge
2
Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance
2
SOURCE-DRAIN DIODE
Symbol IS ISM VSD Parameter
Continuous Source Current ( Body Diode )
Test Conditions VD=VG=0V , VS=-1.2V
1
Min. -
Typ. -0.75
Max. Units -1.8 -20 -1.2 A A V
Pulsed Source Current ( Body Diode )
Forward On Voltage
2
Tj=25C, IS=-1.8A, VGS=0V
Notes:
1.Pulse width limited by max. junction temperature. 2.Pulse width <300us , duty cycle <2%. 3.Surface mounted on FR4 board, t<10sec.
2/10/2005 Rev.2.01
www.SiliconStandard.com
3 of 11
SSM2030GM
N-channel
25 25
T C =25 C
20
o
V G =4.5V V G =3.5V ID , Drain Current (A) V G =3.0V
20
T C =150 o C
V G =4.5V V G =3.5V V G =3.0V
ID , Drain Current (A)
15
15
V G =2.5V
V G =2.5V
10
10
V G =2.0V
5 5
V G =2.0V
0 0 1 2 3 4 5 6
0 0 1 2 3 4 5 6
V DS , Drain-to-Source Voltage (V)
V DS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
45
1.8
40
Id=6A T c =25C
1.6
I D =6A V G =4.5V
35
Normalized RDS(ON)
1.4
RDSON (m )
1.2
30
1.0
25 0.8
20 2 3 4 5
0.6 -50 0 50 100 150
V GS (V)
T j , Junction Temperature ( o C)
Fig 3. On-Resistance vs. Gate Voltage
Fig 4. Normalized On-Resistance vs. Junction Temperature
2/10/2005 Rev.2.01
www.SiliconStandard.com
4 of 11
SSM2030GM
N-channel
8 3
7
6 2 5
ID , Drain Current (A)
4
3 1
2
1
PD (W)
0 25 50 75 100 125 150 0 50 100 150
0
T c , Case Temperature ( o C)
T c ,Case Temperature ( o C)
Fig 5. Maximum Drain Current vs. Case Temperature
Fig 6. Typical Power Dissipation
100
1
DUTY=0.5
Normalized Thermal Response (Rthja)
0.2
1ms
10
0.1
0.1
ID (A)
10ms
0.05
0.02
0.01
100ms
1
P DM
0.01
t T
SINGLE PULSE
T c =25 o C Single Pulse
0.1 0.1 1 10
10us
Duty factor = t/T Peak Tj = PDM x Rthja + Ta
0.001
100
0.0001
0.001
0.01
0.1
1
10
100
1000
V DS (V)
t , Pulse Width (s)
Fig 7. Maximum Safe Operating Area
Fig 8. Effective Transient Thermal Impedance
2/10/2005 Rev.2.01
www.SiliconStandard.com
5 of 11
SSM2030GM
N-channel
6
1000
f=1.0MHz
5
VGS , Gate to Source Voltage (V)
I D =6A V DS =10V Ciss
4
3
C (pF)
Coss
100
Crss
2
1
0 0 2 4 6 8 10 12
10 1 5 9 13 17 21 25 29
Q G , Total Gate Charge (nC)
V DS (V)
Fig 9. Gate Charge Characteristics
Fig 10. Typical Capacitance Characteristics
100.00
1.5
10.00
1
T j =150 o C
1.00
VGS(th) (V)
0.5
IS(A)
T j =25 o C
0.10
0.01 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5
0 -50 0 50 100 150
V SD (V)
T j ,Junction Temperature ( o C)
Fig 11. Forward Characteristic of Reverse Diode
Fig 12. Gate Threshold Voltage vs. Junction Temperature
2/10/2005 Rev.2.01
www.SiliconStandard.com
6 of 11
SSM2030GM
N-channel
VDS
RD
90%
D
VDS
TO THE OSCILLOSCOPE 0.5x RATED VDS
RG
G
+ 4..5V -
S VGS
10% VGS td(on) tr td(off) tf
Fig 13. Switching Time Circuit
Fig 14. Switching Time Waveform
VG
VDS TO THE OSCILLOSCOPE
QG 4.5V
D
G S
+
0.5 x RATED VDS
QGS
QGD
VGS
1~ 3 mA
I
G
I
D
Charge
Q
Fig 15. Gate Charge Circuit
Fig 16. Gate Charge Waveform
2/10/2005 Rev.2.01
www.SiliconStandard.com
7 of 11
SSM2030GM
P-channel
25
25
T C =25 C
20
o
V G =-4.5V V G =-4.0V
20
T C =150 o C
V G =-4.5V
V G =-4.0V V G =-3.5V
-ID , Drain Current (A)
-ID , Drain Current (A)
V G =-3.5V
15
V G =-3.0V
15
V G =-3.0V
10
10
V G =-2.5V
5
V G =-2.5V
5
0 0 1 2 3 4 5 6
0 0 1 2 3 4 5 6
-V DS , Drain-to-Source Voltage (V)
-V DS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
100
1.8
90
Id=-2.2A T c =25C
1.6
I D =-2.2A V G = -4.5V
80
70
Normalized RDS(ON)
1.4
RDSON (m )
1.2
60
1
50
0.8 40
0.6 30 2 3 4 5 -50 0 50 100 150
-V GS (V)
T j , Junction Temperature ( C)
o
Fig 3. On-Resistance vs. Gate Voltage
Fig 4. Normalized On-Resistance vs. Junction Temperature
2/10/2005 Rev.2.01
www.SiliconStandard.com
8 of 11
SSM2030GM
P-channel
6
3
5
2.5
-ID , Drain Current (A)
4
2
PD (W)
3
1.5
2
1
1
0.5
0 25 50 75 100 125 150
0 0 50 100 150
T c , Case Temperature ( o C)
T c ,Case Temperature ( o C)
Fig 5. Maximum Drain Current vs.
Fig 6. Typical Power Dissipation
Case Temperature
100
1
DUTY=0.5
Normalized Thermal Response (R thja)
0.2
1ms
10
0.1
0.1
-ID (A)
10ms
0.05
0.02
0.01
PDM
1
100ms 1s T c =25 o C Single Pulse
0.01
SINGLE PULSE
t T
Duty factor = t/T Peak Tj = P DM x Rthja + Ta
0.1 0.1 1 10 100
0.001 0.0001 0.001 0.01 0.1 1 10 100 1000
-V DS (V)
t , Pulse Width (s)
Fig 7. Maximum Safe Operating Area
Fig 8. Effective Transient Thermal Impedance
2/10/2005 Rev.2.01
www.SiliconStandard.com
9 of 11
SSM2030GM
P-channel
6
10000
f=1.0MHz
5
-VGS , Gate to Source Voltage (V)
I D =-2.2A V DS =-6V
4
1000
Ciss Coss
3
2
C (pF)
100
Crss
1
0 0 2 4 6 8 10 12 14
10 1 5 9 13 17 21 25 29
Q G , Total Gate Charge (nC)
-V DS (V)
Fig 9. Gate Charge Characteristics
Fig 10. Typical Capacitance Characteristics
100.00
1
0.8
10.00
T j =150 o C -VGS(th) (V)
1.3 1.5
-IS(A)
T j =25 o C
1.00
0.6
0.4
0.10
0.2
0.01 0.1 0.3 0.5 0.7 0.9 1.1
0 -50 0 50 100 150
-V SD (V)
T j ,Junction Temperature ( o C)
Fig 11. Forward Characteristic of Reverse Diode
Fig 12. Gate Threshold Voltage vs. Junction Temperature
2/10/2005 Rev.2.01
www.SiliconStandard.com
10 of 11
SSM2030GM
P-channel
VDS
RD
90%
D
VDS
TO THE OSCILLOSCOPE 0.5 x RATED VDS
RG
G
10%
S -4.5 V VGS
VGS td(on) tr td(off) tf
Fig 13. Switching Time Circuit
Fig 14. Switching Time Waveform
VG
VDS TO THE OSCILLOSCOPE
QG -4.5V
D
G S -1~-3mA I
G
0.3 x RATED VDS
QGS
QGD
VGS
ID
Charge
Q
Fig 15. Gate Charge Circuit
Fig 16. Gate Charge Waveform
Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties.
2/10/2005 Rev.2.01
www.SiliconStandard.com
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